1. Field of the Invention
The present invention relates to package structures, and, more particularly, to a single-layered package structure and a method of fabricating the same.
2. Description of Related Art
With the advancement in the technology of semiconductor package, various semiconductor devices have been developed and incorporated in smart phones, tablets, internet, and notebooks in a variety of forms, such as ball grid array (BGA), Quad-Flat Package (QFP) or Quad Flat Nonlead Package (QFN).
As shown in FIG. 1A, a conventional QFP package structure 1 comprises: a carrier 10, a plurality of leads 11 surrounding the carrier 10, an electronic component 12 adhered to the carrier 10 and electrically connected to the leads 11 by a plurality of bonding wires 120, and an insulative layer 13 such as an encapsulant that encapsulates the electronic component 12, the carrier 10, the bonding wires 120 and the leads 11, wherein the leads 11 protrude from the insulative layer 13.
However, in the conventional method of fabricating the QFP package structure 1, the carrier 10 and the leads 11 are structured into a leadframe. Therefore, the wiring arrangement, including the layout of wiring and I/O connections, is restricted. For instance, in a conventional leadframe, the number of I/O components and pitch of the leads 11 are restricted by the total length of leads 111 arranged in row which is around 400 μm and the total length of the carrier 10 which is 125 μm.
Moreover, during the packaging process, owing to the fixed size of the leadframe and the height of the bonding wires 120, the overall size of QFP package structure 1 could not be thinner.
Moreover, in a conventional QFP package structure 1, owing to the design of the leadframe, the number of leads 11, i.e., the I/O contacts are less, and it is difficult to meet the demand for high I/O connections and low profile.
As shown in FIG. 1B, a conventional BGA package structure 1′ allows more I/O connections to be incorporated in a same unit area of a package substrate, for meeting the requirement for a chip with high integration. The package structure 1′ comprises a carrier 10′ having a wiring layer 11a, 11b on the top side 10a and bottom side 10b thereof; an electronic component 12 disposed on the top side 10a of the carrier 10′ and electrically connected to the wiring layer 11a via a plurality of conductive bumps 120′; an insulative layer 13 such as an underfill that encapsulates the conductive bumps 120′; and conductive elements 14 such as solder balls formed on the wiring layer 11b of the bottom side 10b of the carrier 10′. The conductive pillars 100 are electrically connected with the wiring layer 11a, 11b. After the electronic component 12 is electrically connected to the carrier 10′ by wire bonding or flip chip method, conductive elements 14 are formed on the wiring layer 11 b of the bottom side 10b of the carrier 10′ for forming external electrical connections, so as to reach high number of leads.
However, the conventional BGA package structure 1′ still poses a problem that the signal transmission path (formed by the conductive elements 14, the wiring layers 11a and 11b, and conductive pillars 100) is too long, whereby the electrical performance of the package structure 1′ during high frequency use or high operational speed is undesirably limited.
Moreover, the conventional BGA package structure 1′ requires fabricating at least two wiring layers 11a and 11b and the conductive pillars 100 (such as drilling, platting copper materials in vias for forming electrical connections between the two layers). Thus, it is difficult for the overall structure to meet the low profile requirement, and hard to reduce the fabricating cost due to the complexity of the fabricating process.
In addition, the conventional BGA package structure 1′ requires many interfaces to be fabricated (such as those between the conductive elements 14, wiring layer 11a,11b and conductive pillars 100), as well as using a hybrid carrier 10′ having a plurality of layers made of different materials, whereby delamination tends to incur and is undesirably increased.
Further, as the carrier 10′ is composed of multiple layers made of different materials, the thermal expansion coefficient (CTE) of each layer is different. As a result, CTE mismatch would result in warpage during the fabricating process.
Therefore, there is an urgent need in solving the foregoing problems.